1. Technical Field of the Invention
The present invention relates to constructions and manufacturing methods of semiconductor devices in which a p-channel and n-channel thin-film transistors are arranged on a common substrate. More particularly, the invention is concerned with circuit configurations and manufacturing methods of complementary metal oxide semiconductor (CMOS) devices comprising thin-film transistors arranged on a glass substrate.
2. Description of the Related Art
In one conventionally known technique used for producing a thin-film transistor, a silicon layer is formed on a glass substrate and this silicon layer is used for manufacturing the thin-film transistor. This prior art technique has evolved mostly in the industry of manufacturing active matrix liquid crystal display devices.
Generally, a liquid crystal display is so constructed that liquid crystal is sandwiched between a pair of glass substrates. When voltages are applied across the liquid crystal layer which constitutes a large number of pixels arranged in a matrix form, optical properties of the liquid crystal are varied. As a result, the liquid crystal display presents a picture corresponding to the applied voltages.
An active matrix liquid crystal display is generally so constructed that thin-film transistors are provided in the aforementioned pixels which are arranged in a matrix form. These thin-film transistors control electric charges which are fed into and output from the individual pixels.
A common construction of the active matrix liquid crystal display today is such that a circuit (which is referred to as a peripheral driver circuit) for driving thin-film transistors arranged in a few hundred rows by a few hundred columns in an active matrix area is composed essentially of an integrated circuit (a driver IC) which is connected to the outside of a glass substrate using tape automated bonding (TAB) technology, for instance.
One problem of this construction, in which the driver IC is externally mounted to the outside of a glass substrate, is that it requires a complicated process for producing active matrix liquid crystal displays. For example, alignment of each driver IC and operational tests become complicated. Another problem is that a projecting portion is created on each active matrix liquid crystal display when the driver IC is externally mounted. This will impair potential multi-purpose applicability of the active matrix liquid crystal displays in cases where they are to be assembled into various kinds of electronics apparatus.
An approach to the solution of the aforementioned problems is to integrally form a peripheral driver circuit itself with thin-film transistors directly on a glass substrate. This approach makes it possible to create an integrated device structure. Furthermore, it will provide such advantageous effects as simplification of manufacturing processes, increased reliability and greater applicability.
In an active matrix liquid crystal display having such an integrally formed peripheral driver circuit, a CMOS circuit is required to configure the peripheral driver circuit. The CMOS circuit is one of basic electronic circuits in which n- and p-channel transistors are joined together to form a complementary configuration.
An example of a conventional method of producing CMOS circuitry on a glass substrate is described with reference to FIGS. 4(A) to 4(D).
First, a silicon oxide film 402 which constitutes an underlying layer is grown on a glass substrate 401 as shown in FIG. 4(A). Then, active layers 403 and 404 which may either be crystalline or amorphous silicon layers are deposited on top of the silicon oxide film 402, and another silicon oxide film 405 which covers the active layers 403 and 404 and acts as a gate insulating layer is created. In FIG. 4(A), the active layer 403 is an islandlike region forming an active layer of an n-channel thin-film transistor while the active layer 404 is an islandlike region forming an active layer of a p-channel thin-film transistor.
Next, gate electrodes 406 and 407 composed of an electrically conductive material such as a silicide are formed as shown in FIG. 4(B), and phosphorus ions are implanted over the whole surface of the workpiece shown in FIG. 4(C). As a result, portions designated by the numerals 408, 410, 411 and 413 become n-type regions. The implantation of phosphorus ions is performed at a dose of 1xc3x971015/cm2 to 2xc3x971015/cm2 under conditions where a surface phosphorus ion density of 1xc3x971020/cm2 or over is achieved.
Subsequently, a resist mask 414 is formed to selectively cover the n-channel thin-film transistor and boron ions are implanted as shown in FIG. 4(D) at a dose three to five times higher than the aforesaid dose of phosphorus ions. This causes the n-type regions 411 and 413 (FIG. 4(C)) to turn to the opposite conductivity type, or p-type. A source region 415, a drain region 416 and a channel region 412 of the p-channel thin-film transistor are created in a self-aligned manner. The reason why such a heavy doping level as described above is required is that the regions 415, 412 and 416 must form a p-i-p junction. In the construction of FIG. 4(D), the numerals 408, 409 and 410 designate a source region, a channel region and a drain region of the n-channel thin-film transistor, respectively.
In the aforementioned production method there is no need to form a resist mask in the processing step shown in FIG. 4(C). Although this is advantageous for simplifying production process, the production method has the following problems.
First, the implantation of impurity ions into the resist mask 414 at an extremely high doping level causes resist materials to vary in their properties, and this will result in an increase in the probability of occurrence of failures in the production process. More specifically, it may become impossible to remove the resist materials after doping, or the resist materials may partially be left after a photoresist removal process.
Second, the existence of an off current flowing through a junction between the channel region 412 and drain region 416 can not be disregarded. This is because the drain region 416 adjacent to the channel region 412 of the p-channel thin-film transistor shown at right in FIG. 4(D) is a region doped with an extremely high concentration of impurities, in which the impurity ions are added at a far higher doping level than what is normally required for producing a p-channel device, in order to invert the conductivity type.
Third, the boron ions implanted are inevitably added to the channel region 412 in part due to their undesirable migration. This phenomenon gives rise to a problem that essential electrical properties are not obtained at all, or such electrical properties are often unattainable.
Fourth, the implantation of the impurity ions at a high doping level which is needed in the processing step shown in FIG. 4(D) may overload an ion implanter or a plasma doping machine. This is likely to arise various problems due to contamination inside the equipment and its maintenance.
A fifth problem is that the need for the implantation of the impurity ions at a high doping level may lead to an increase in processing time.
A sixth problem could develop when annealing a product by using laser light. Generally, the resist mask 414 is removed after the processing step shown in FIG. 4(D) is finished, and then an annealing process, in which a laser beam is irradiated upon the product, is required in order to activate the dopant and to anneal the regions where the impurity ions have been implanted. (This method is effective when a glass substrate having low thermal resistance is used.) Since the regions 415 and 416 are doped with far larger amounts of impurity ions compared to the regions 408 and 410, remarkable damage occurs in the crystallinity of the former regions. Consequently, the dependence of optical absorbance on wavelength greatly differs between the two groups of regions: the regions 408 and 410, and the regions 415 and 416. In this situation, the effect of annealing by the laser light also differs considerably between the two groups of regions. This is not preferable because a large difference in electrical properties will occur between the n-channel thin-film transistor and p-channel thin-film transistor shown at left and right in FIG. 4(D), respectively.
It is a general object of the invention to provide a solution to the aforementioned problems which arise when n- and p-channel thin-film transistors are created at the same time by implanting impurity ions at a high doping level.
A more specific object of the invention is to compensate for adverse effects of a difference in electrical properties between the n- and p-channel thin-film transistors when configuring CMOS circuitry with thin-film transistors, and thereby provide a high-performance CMOS circuit.
According to the invention, a semiconductor device comprises an n-channel thin-film transistor (NTFT) and a p-channel thin-film transistor (PTFT) integrally produced on a single substrate, in which a lightly-doped drain (LDD) region is formed selectively in the n-channel thin-film transistor, a source region and a drain region of the p-channel thin-film transistor are doped with only those impurities which produce p-conductivity, and regions doped with impurities which produce n-conductivity and p-conductivity are formed adjacent to the source region and drain region of the p-channel thin-film transistor.
As will be later described in detail with reference to a specific embodiment. By way of example, in FIG. 3(B), a CMOS circuit is configured with an n-channel thin-film transistor located on the left side and a p-channel thin-film transistor located on the right side. In this CMOS circuit structure, a lightly-doped drain region 124 composed of a low dopant concentration region is provided just between a channel region and a drain region of only the left-hand n-channel thin-film transistor. The lightly-doped drain region serves to reduce off current and suppress deterioration by moderating a field strength applied between the channel region and drain region. It also serves to substantially decrease carrier mobility in a thin-film transistor by increasing the resistance between its source and drain.
When silicon is used as a semiconductor, a typical example of impurity for providing p-conductivity is phosphorus (P). A typical example of impurity for providing p-conductivity when using silicon as a semiconductor is boron (B).
The p-channel thin-film transistor of the above CMOS circuit structure in FIG. 3 is not provided with any particular buffering region like the lightly-doped drain region. There are, however, provided offset gate regions in the n- and/or p-channel thin-film transistor by using an insulating film produced on a side surface of each gate electrode. The offset gate regions exhibit similar effects to the lightly-doped drain region.
In the later-described embodiment, in FIG. 1(E), anodic oxide films 114 and 115 act as a mask when impurity ions are implanted, and offset gate regions having a width approximately equal to the thickness of the anodic oxide films, as measured at side surfaces of the gate electrode, are produced. These offset gate regions do not function as effective offset gate regions, however, if their width is too small.
Other important features of the semiconductor device of the invention are as follows. In a process shown as FIG. 1(E), regions 128 and 130 undoped in a phosphorus ion doping process as they are masked by the anodic oxide films 112 and 113 are doped with boron ions in a later doping process of FIG. 2(C) (referred as FIG. 3(B)). Accordingly, these regions contain only such impurities that produce p-conductivity. The inventors refer to these regions 128 and 130, respectively, in the p-channel thin-film transistor as source and drain regions.
To add, regions 127 and 131 adjacent to the source and drain regions 128, 130 are doped with phosphorus ions in the aforementioned phosphorus ion doping process of FIG. 1(E). Accordingly, these regions contain both types of impurities that produce n-conductivity and p-conductivity. The inventors clearly discriminate these regions 127 and 131 from the source region 128 and drain region 130 and refer to them as contact pads because they act only as connecting electrodes that make electrical contact to the source and drain regions.
The semiconductor device of the invention is therefore characterized in that the source region and drain region of the p-channel thin-film transistor are individually sandwiched between one of the regions doped with the impurities which produce n-conductivity and p-conductivity and a channel region.
If the channel region of the n- and/or p-channel thin-film transistors is doped with impurities that produce a single conductivity type, it becomes possible to effectively control threshold voltage, which is one of important electrical properties of thin-film transistors. This is achieved by adding boron ions that produces p-conductivity to the channel region of the n-channel thin-film transistor and phosphorus ions that produces n-conductivity to the channel region of the p-channel thin-film transistor, for instance.
In a varied form of the invention, a semiconductor device comprises an n-channel thin-film transistor and a p-channel thin-film transistor integrally produced on a single substrate, in which an offset gate region is formed in the n-channel thin-film transistor, the offset gate region having a larger width than an offset gate region formed in the p-channel thin-film transistor, a source region and a drain region of the p-channel thin-film transistor are doped with only those impurities which produce p-conductivity, and regions doped with impurities which produce n-conductivity and p-conductivity are formed adjacent to the source region and drain region of the p-channel thin-film transistor.
In another varied form of the invention, a semiconductor device comprises an active matrix area containing n-channel thin-film transistors arranged in a matrix form and a peripheral driver circuit for driving the n-channel thin-film transistors of the active matrix area, the active matrix area and the peripheral driver circuit being produced on a single substrate, in which the peripheral driver circuit incorporates a circuit including n- and p-channel thin-film transistors which are interconnected to form a complementary configuration, a lightly-doped drain region and/or an offset gate region is formed selectively in each n-channel thin-film transistor of the peripheral driver circuit, a source region and a drain region of each p-channel thin-film transistor of the peripheral driver circuit are doped with only those impurities which produce p-conductivity, and regions doped with impurities which produce n-conductivity and p-conductivity are formed adjacent to the source region and drain region.
In still another varied form of the invention, a semiconductor device comprises an active matrix area containing p-channel thin-film transistors arranged in a matrix form and a peripheral driver circuit for driving the p-channel thin-film transistors of the active matrix area, the active matrix area and the peripheral driver circuit being produced on a single substrate, in which the peripheral driver circuit incorporates a circuit including n- and p-channel thin-film transistors which are interconnected to form a complementary configuration, a lightly-doped drain region and/or an offset gate region is formed selectively in each n-channel thin-film transistor of the peripheral driver circuit, a source region and a drain region of each p-channel thin-film transistor of the active matrix area and peripheral driver circuit are doped with only those impurities which produce p-conductivity, and regions doped with impurities which produce n-conductivity and p-conductivity are formed adjacent to the source region and drain region.
According to the invention, a method of manufacturing a semiconductor device in which an n-channel thin-film transistor and a p-channel thin-film transistor are integrally produced on a single substrate comprises a first process of selectively forming anodic oxide films having a porous structure on side surfaces of gate electrodes composed of a material that can be anodized, a second process of adding impurities which produce n-conductivity using the anodic oxide films as a mask, a third process of removing the anodic oxide films, a fourth process of selectively masking an area where the p-channel thin-film transistor is produced with a photoresist, a fifth process of adding impurities which produce n-conductivity using the gate electrodes and the photoresist applied in the fourth process as a mask to form lightly-doped drain regions beneath areas where the anodic oxide films existed, a sixth process of removing the photoresist applied in the fourth process, a seventh process of selectively masking an area where the n-channel thin-film transistor is produced with a photoresist, and an eighth process of adding impurities which produce p-conductivity using the gate electrodes and the photoresist applied in the seventh process as a mask, wherein regions doped with only the impurities which produce p-conductivity are formed in the eighth process beneath areas where the anodic oxide films existed, while regions doped with the impurities which produce n-conductivity and p-conductivity are formed adjacent to the regions doped with only the impurities which produce p-conductivity.
The impurities for producing either n-conductivity or p-conductivity are added by injecting accelerated impurity ions through a gate insulating layer in the aforementioned second, fifth and eighth processes. This serves of reduce damages to active layers of the thin-film transistors.
Another method of manufacturing a semiconductor device in which an n-channel thin-film transistor and a p-channel thin-film transistor are integrally produced on a single substrate comprises a first process of selectively forming anodic oxide films having a porous structure on side surfaces of gate electrodes composed of a material that can be anodized, a second process of adding impurities which produce n-conductivity using the anodic oxide films as a mask, a third process of removing the anodic oxide films, a fourth process of selectively masking an area where the n-channel thin-film transistor is produced with a photoresist, and a fifth process of adding impurities which produce p-conductivity using the gate electrodes and the photoresist as a mask, wherein an offset gate region having a width determined by the anodic oxide films having the porous structure is selectively formed in the n-channel thin-film transistor in the second process.
What is characteristic of the above construction as it is applied to one specific embodiment shown as FIG. 5 is that a physical dimension of offset gate regions 515 and 517 is determined by the width of an anodic oxide film 505 having a porous structure. If another anodic oxide film 500 of a fine and dense structure has a large thickness, it will also contribute to the formation of the offset gate regions 515 and 517.
In one modified method of manufacturing a crystalline silicon film, the crystalline silicon film used for making active layers of the n- and p-channel thin-film transistors is produced by a process comprising a first step of forming a metallic element for accelerating crystallization on an amorphous silicon film, a second step of converting the amorphous silicon film into a crystalline silicon film by heat treatment, a third step of forming a thermal oxide layer on top of the crystalline silicon film by heating it in an atmosphere containing a halogen element, and a fourth step of removing the thermal oxide layer, wherein the metallic element remaining in the crystalline silicon film is absorbed into the thermal oxide layer by gettering operation performed in the third step.
Preferably, the aforementioned second step is performed within a temperature range of 500 to 700xc2x0 C. and the third step is performed within a temperature range of 700 to 1200xc2x0 C.
The present invention is described in detail in the embodiments 1 to 10 as follows.